Raspberry SoC 스펙

• SoC: BCM2837
  • Silicon die: BCM2710
  • ARM Core
    • CPU Family: ARM Coretex-A53 (64bit ARMv8-A 아키텍처)
    • Quad-core (1.2Ghz)
    • Spupport 40bit physical address
  • GPU Core
    • BCM VideoCore IV @ 300 MHz
  • L1 Cache
    • Instruction Cache
      • 32KB(VIPT, 2 way, 64 bytes per cache line)
    • Data Cache
      • 32KB(PIPT, 4 way, 64 bytes per cache line) with STB(merging STore Buffer)
      • MOESI cache coherent between cores
  • L2 Cache:
    • Unification(I+D) Cache
      • 512KB for ARM(16 way, 64 bytes per cache line)
  •  TLB
    •  micro-TLB
      • micro I-TLB
        • fully-associative 10 entry
      • micro-D-TLB
        • fully-associative 10 entry
    • Unified Main TLB
      • 4-way 512 entry
      • 4-way 64 entry walk cache
      • 4-way 64 entry IPA(Intermediate Physical Address) cache
•  RAM
  • 1GB LPDDR2 (GPU랑 공유)

(iamroot 12차-A팀 공식 추천 보드)

• SoC: BCM2836
  • Silicon die: BCM2709
  • ARM Core
    • CPU Family: ARM Coretex-A7 (ARMv7-A 아키텍처)
    • Quad-core (900Mhz)
  • GPU Core
    • BCM VideoCore IV @ 250 MHz
  • L1 Cache
    • Instruction Cache
      • 32KB(TCM, VIPT, 2 way, 32 bytes per cache line)
    • Data Cache
      • 32KB(PIPT, 4 way, 64 bytes per cache line) with STB(merging STore Buffer)
  • L2 Cache:
    • Unification(I+D) Cache
      • 512KB for ARM(2~3 clock, 8 way, 64 bytes per cache line)
      • 128KB for GPU
  •  TLB
    •  micro-TLB
      • micro I-TLB
      • micro-D-TLB
    • Main TLB
  • Branch Prediction:
    • BTIC(Branch Target Instruction Cache): 4 entries(1 entry have 2 instructions)
    • BTAC(Branch Target Address Cache): 8 entries
    • Branch Prediction: 256 entries
    • Return Stack: 8 entries
  • TCM
    • No TCM for 2 DMA channels
•  RAM
  • 1GB (GPU랑 공유)

라즈베리 파이(Raspberry Pi 모델B 또는 B+)

• SoC: BCM2835
  • Silicon die: BCM2708
  • ARM Core
    • CPU Family: ARM1176JZF-S (ARMv6z 아키텍처)
    • Single-core (700Mhz)
  • GPU Core
    • BCM VideoCore IV @ 250 MHz
  • L1 Cache
    • Instruction Cache
      • 16KB(TCM, VIPT, 4 way, 32 bytes per cache line)
    • Data Cache
      • 16KB(3 cycle, VIPT, 4 way, 32 bytes per cache line)
  • L2 Cache
    • Unification(I+D) Cache
      • Share 128KB for ARM & GPU
  • TLB
    • micro-TLB
      • micro I-TLB(1 cycle, 10 entries),
      • micro-D-TLB(1 cycle, 10 entries)
    • Main TLB
      • 64 low entries 2 way + 8 full entries
  • Brqnch Prediction
    • BTAC: 128 entries
  • TCM
    •  Instruction-TCM
    • Data-TCM
      • 8KB for 2 DMA channels
• RAM
  • 512MB (GPU랑 공유)